The present invention relates to integrated circuit wire routing, and more specifically, to a method for modeling integrated circuit congestion and wire distribution in three dimensions (3D) using two-dimensional (2D) global routing.
Routing of wires on an integrated circuit (IC) is an important VLSI (very large integrated circuit) design phase. A two-step approach to routing has often been implemented in which an initial global routing solution is followed by a detailed routing solution. Global routing may define routing regions over the integrated circuit, generate tentative routes for each net from a driver to a receiver, and assign each tentative net to a set of routing regions. Actual placement of wires, layout of routing tracks and assignment of wires to specific tracks is performed during the subsequent detailed routing.
Global routing may include two-dimensional (2D), computer-based modeling of congestion, that is, blockage of tracks. Blockage may include, for example, tracks previously assigned or used at a lower level of the design hierarchy, so-called “third-party IP,” contacts to and from lower or higher hierarchies, and pre-routed wires (for example, wires predetermined as power wires).
During global routing, all layers of a multilayered integrated circuit may be segregated into a continuous 2D array of “tiles,” or global routing cells (“Gcells”) for the purpose of creating a mathematical model of the integrated circuit wiring. However, the results of 2D modeling regarding congestion has not been accurate.
As a result, three-dimensional (3D) modeling regarding congestion in multiple layers of an integrated circuit has been required during the detailed routing phase in order to provide a sufficiently accurate model for detailed design purposes. However, 3D modeling requires the use of relatively complicated algorithms that are require relatively high usage of computational resources.